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128Kx32 CMOS High Speed Static RAM
FEATURES
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EDI8L32128C
DESCRIPTION
The EDI8L32128C is a high speed, high performance, four megabit density Static RAM organized as a 128Kx32 bit array. Four Chip Enables, Write Control, and Output Enable provide the user with a flexible memory solution. The user may independently enable each of the four bytes, and, with minimal additional peripheral logic, the unit may be configured as a 256Kx16 or 512Kx8 array. Fully asynchronous circuitry is used, requiring no clocks or refreshing for operation and providing equal access and cycle times for ease of use. The EDI8L32128C, allows 4 megabits of memory to be placed in less than 0.990 square inches of board space; a savings of 0.885 square inches over four standard 128Kx8 components.
NOTE: Solder Reflow temperature should not exceed 230C
T NO
128Kx32 bit CMOS Static Random Access Memory Array Fast Access Times: 12, 15, 17, 20, and 25ns Individual Byte Enables User Configurable Organization with Minimal Additional Logic Master Output Enable and Write Control TTL Compatible Inputs and Outputs Fully Static, No Clocks
D DE EN M M CO RE
TOP VIEW
1
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Surface Mount Package
68 Lead PLCC, No. 99 (JEDEC MO-47AE) Small Footprint, 0.990 Sq. In. Multiple Ground Pins for Maximum Noise Immunity n Single +5V (5%) Supply Operation
FIG. 1 PIN CONFIGURATION
PIN DESCRIPTION
AO-16 EO-3 W G Address Inputs Chip Enables (One per Byte) Master Write Enable Master Output Enable Common Data Input/Output Power (+5V5%) Ground No Connection
NOTE: Pin 2 & 67 on the 64Kx32 (EDI8L3265C) and the 256Kx32 (EDI8L32256C) are word select pins.
R FO
DQO-31 VCC VSS NC
W NE
BLOCK DIAGRAM
GN SI DE
August 2002 Rev. 6 ECO #15423
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ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature Power Dissipation Output Current. Junction Temperature, TJ -0.5V to 7.0V 0C to + 70C -40C to +85C -55C to +125C 4 Watts 20 mA 175C Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Sym VCC VSS VIH VIL
EDI8L32128C
RECOMMENDED DC OPERATING CONDITIONS
Min 4.75 0 2.2 -0.3 Typ 5.0 0 --Max 5.25 0 VCC+0.5 0.8 Units V V V V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (f = 1.0MHz, VIN = VCC or VSS)
Parameter Address Lines Data Lines Write & Output Enable Lines Chip Enable Lines/Byte Select Sym CA CD/Q W, G E0-3 Max 40 10 40 8 Unit pF pF pF pF
TRUTH TABLE
E H L L L L W X H X H L G X H X L X Mode Standby Output Disable Output Disable Read Write Output High Z High Z High Z DOUT DIN Power ICC2,ICC3, ICC1 ICC1 ICC1 ICC1
DC ELECTRICAL CHARACTERISTICS
Parameter Operating Power Supply Current Standby (TTL) Supply Current Full Standby CMOS Supply Current Input Leakage Current Output Leakage Current Output High Volltage Output Low Voltage
Typical: TA = 25C, VCC = 5.0V
Sym ICC1 ICC2 ICC3 ILI ILO VOH VOL
Conditions W= VIL, II/O = 0mA, Min Cycle E VIH, VIN VIL or VIN VIH, f = OMHz E VCC -0.2V VIN VCC -0.2V or VIN 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH = -4.0mA IOL = 8.0mA
Typ 620
12* 720 160 20
15 680 160 20
Max
17 640 160 20 10 10 0.4
20/25 600 160 20
Units mA mA mA A A V V
2.4
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V Figure 2
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 3)
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AC CHARACTERISTICS - READ CYCLE
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1)
NOTE 1: Parameter guaranteed, but not tested.
EDI8L32128C
Symbol JEDEC Alt. tAVAV tRC tAVQV tAA tELQV tACS tELQX tCLZ tEHQZ tCHZ tAVQX tOH tGLQV tOE tGLQX tOLZ tGHQZ tOHZ
12ns 15ns 17ns 20ns 25n Min Max Min Max Min Max Min Max Min Max Units 12 15 17 20 25 ns 12 15 17 20 25 ns 12 15 17 20 25 ns 2 3 3 3 3 ns 7 8 8 10 10 ns 3 3 3 3 3 ns 5 6 8 8 10 ns 2 2 2 2 0 ns 4 5 6 8 10 ns
FIG. 4 READ CYCLE 1 - W HIGH, G, E LOW
FIG. 5 READ CYCLE 2 - W HIGH
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AC CHARACTERISTICS - WRITE CYCLE
Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1)
NOTE: Parameter guaranteed, but not tested.
EDI8L32128C
Symbol JEDEC Alt. tAVAV tWC tCW tELWH tELEH tCW tAVWL tAS tAVEL tAS tAW tAVWH tAVEH tAW tWLWH tWP tWLEH tWP tWHAX tWR tEHAX tWR tWHDX tDH tEHDX tDH tWLQZ tWHZ tDVWH tDW tDVEH tDW tWHQX tWLZ
12ns Min Max 12 8 8 0 0 9 9 9 9 0 0 0 0 0 5 5 5 2
15ns Min Max 15 9 9 0 0 10 10 10 10 0 0 0 0 0 6 6 6 2
Min 17 10 10 0 0 12 12 12 12 0 0 0 0 0 8 8 2
17ns Max
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20ns Min Max 20 15 15 0 0 15 15 15 15 0 0 0 0 0 7 8 8 2
25ns Min Max 25 20 20 0 0 15 15 15 15 0 0 0 0 0 10 12 12 2
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
FIG. 6 WRITE CYCLE 1 - W CONTROLLED
FIG. 7 WRITE CYCLE 2 - E CONTROLLED
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PACKAGE DESCRIPTION
PACKAGE NO. 99: 68 LEAD PLCC JEDEC MO-47AE
EDI8L32128C
ORDERING INFORMATION
Commercial (0C to +70C) Part Number EDI8L32128C12AC EDI8L32128C15AC EDI8L32128C17AC EDI8L32128C20AC EDI8L32128C25AC Speed (ns) 12 15 17 20 25 Package No. 99 99 99 99 99
T NO
D DE EN M M CO RE
ALL DIMENSIONS ARE IN INCHES
R FO
Industrial (-40C to +85C) Part Number EDI8L32128C15AI EDI8L32128C17AI EDI8L32128C20AI
W NE
Speed (ns) 15 17 20
Package No. 99 99 99
GN SI DE
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